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S71NS-N MCP Products
MirrorBit(R) 1.8 Volt-only Simultaneous Read/Write, Burst-mode Multiplexed Flash Memory
256 Mb (16 Mb x 16-bit), 128 Mb (8 Mb x 16-bit) and 64 Mb (4 Mb x 16-bit) with Multiplexed pSRAM 64 Mb (4 Mb x 16-bit), 32 Mb (2 Mb x 16-bit), 16 Mb (1 Mb x 16-bit) and 8Mb (512Kb x 16-bit)
Data Sheet (Advance Information)
S71NS-N MCP Products Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S71NS-N_00
Revision A
Amendment 7
Issue Date March 26, 2008
Data
Sheet
(Advance
Information)
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination
Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local sales office.
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S71NS-N MCP Products
S71NS-N_00_A7 March 26, 2008
S71NS-N MCP Products
MirrorBit(R) 1.8 Volt-only Simultaneous Read/Write, Burst-mode Multiplexed Flash Memory
256 Mb (16 Mb x 16-bit), 128 Mb (8 Mb x 16-bit) and 64 Mb (4 Mb x 16-bit) with Multiplexed pSRAM 64 Mb (4 Mb x 16-bit), 32 Mb (2 Mb x 16-bit), 16 Mb (1 Mb x 16-bit) and 8Mb (512Kb x 16-bit)
Data Sheet (Advance Information)
Features
Power supply voltage of 1.7 V to 1.95 V Burst Speed: 66 MHz Package - MCP BGA: 0.5 mm ball pitch
- 8.0 x 9.2 mm, 56 ball for NS064N and NS128N based MCPs - 10.0 x 11.0 mm, 60 ball for NS256N based MCPs
Operating Temperature
- Wireless, -25C to +85C
General Description
The S71NS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists of the following items: One or more S29NS-N flash memory die Mux burst-mode pSRAM The products covered by this document are listed in the table below. For details about their specifications, please refer to their individual datasheet for further details.
pSRAM Density 64 Mb Flash 128 Mb (1) 256 Mb (1) Note 1. Not recommended for new designs. Use S71NS128P and S71NS256P instead. 8 Mb S71NS064N80 (1) 16 Mb S71NS064NA0 S71NS128NA0 32 Mb S71S064NB0 S71NS128NB0 S71NS256NB0 S71NS128NC0 S71NS256NC0 64 Mb
For detailed specifications, please refer to the individual data sheets:
Document S29NS-N 8 M Multiplexed pSRAM Type 1 16 M Multiplexed pSRAM Type 1 32 M Multiplexed pSRAM Type 3 64 M Multiplexed pSRAM Type 3 Publication Identification Number S29NS-N_00 muxpSRAM_06 muxpSRAM_00 muxpsram_04 muxpsram_01
Publication Number S71NS-N_00
Revision A
Amendment 7
Issue Date March 26, 2008
This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.
Data
Sheet
(Advance
Information)
1.
Ordering Information
The order number is formed by a valid combinations of the following:
S71NS
128
N
C
0
BJ
W
R
N
0 Packing Type 0 = Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel RAM Supplier and Speed Combinations N = pSRAM Type 3, 70 ns, 66 MHz A = pSRAM Type 1, 70 ns, 66 MHz Package Modifier R = 1.2 mm, 8.0 x 9.2, 56-ball VFBGA V = 1.2 mm, 11 x 10 mm, 60-ball VFBGA Temperature Range W = Wireless (-25C to +85C) Package Type BJ = Very Thin Fine-Pitch Ball Grid Array (VFBGA) Lead (Pb)-free Package (LF35) BH = Very Thin Fine-Pitch Ball Grid Array (VFBGA) Lead (Pb)-free, LowHalogen Package Chip Contents--2 No Content pSRAM Density C = 64 Mb B = 32 Mb A = 16 Mb 8 = 8 Mb Process Technology N = 110 nm MirrorBit Technology Flash Density 256 = 256 Mb 128 = 128 Mb 064 = 64 Mb Product Family Multi-Chip Product 1.8 Volt-only Simultaneous Read/Write Burst Mode Multiplexed Flash Memory + pSRAM
1.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Table 1.1 MCP Configurations and Valid Combinations
Base Ordering Part Number (1) S71NS064N80 S71NS064NA0 S71NS064NB0 S71NS128NA0 (2) S71NS128NB0 (2) S71NS128NC0 (2) S71NS256NB0 (2) S71NS256NC0 (2) BJW BJW, BHW RN UN RN RN RN VN VN 0, 2, 3 pSRAM Type 3 pSRAM Type 1 pSRAM Type 3 pSRAM Type 3 pSRAM Type 3 pSRAM Type 3 pSRAM Type 3 66 MHz Flash 66 MHz/ Asynchronous pSRAM 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz Package & Temperature Model Number RA RA Packing Type pSRAM Type pSRAM Type 1 pSRAM Type 1 Flash Speed Options pSRAM Speed Options
66 MHz 66 MHz
Note 1. The package marking omits the leading S from the ordering part number. 2. Products no longer recommended for new designs. Please contact local Spansion sales representative for recommended migratory path.
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2.
Input/Output Descriptions
Table 2.1 identifies the input and output package connections provided on the device. Table 2.1 Input/Output Descriptions
Symbol AMAX - A16 ADQ15 - ADQ0 OE# WE# VSS NC RDY Address inputs Multiplexed Address/Data Output Enable input. Asynchronous relative to CLK for the Burst mode. Write Enable input. Ground No Connect; not connected internally Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY. Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode Address Valid input. Indicates to device that the valid address is present on the address inputs. AVD# Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs F-RST# F-WP# Hardware reset input. Low = device resets and returns to reading array data Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. Chip-enable input for pSRAM. Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode. Control Register Enable (pSRAM). Flash 1.8 Volt-only single power supply. pSRAM Power Supply. Upper Byte Control (pSRAM). Lower Byte Control (pSRAM) Do Not Use X X X X X X X X X X Description Flash X X X X X X X RAM X X X X X X X
CLK
X
X
F-ACC R-CE1# F-CE# R-CRE F-VCC R-VCC R-UB# R-LB# DNU
X X
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3.
MCP Block Diagram
Figure 3.1 MCP Block Diagram
F-RST# F-ACC F-WP# F-CE # OE# WE# AVD # CLK Amax-A16
RST# ACC WP# CE# OE# WE# AVD # CLK Amax-A16
NS
RDY AD15-AD0
RDY/ WAIT AD15-AD0
R-CE# R-CRE R-UB # R-LB #
OE# WE# AVD # CLK CE # CRE UB # LB#
pSRAM
WAIT
AD15-AD0
Amax-A16
Note The CLK and WAIT signals on the pSRAM are not present on the pSRAM Type 2; therefore, for those MCP's, those signals will only be connected to the NS flash, but not to the pSRAM. Also, on this pSRAM, the CRE signal will not be present at all.
4. Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S71NS-N.
4.1
Special Handling Instructions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
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4.2
4.2.1
Connection Diagrams
pSRAM Based Pinout, 56-Ball, VFBGA
Figure 4.1 pSRAM Based Pinout, 56-Ball, VFBGA
56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
Legend
A1 NC
A14 NC
No Connect (Distance between outer NC balls is 2x pitch)
C3
C4
C7
C8
C11
C12
NC
D3
RFU
D4 D5 D6
R-LB#
D7
R-UB#
D8 WE# E8 F-RST# F8 A/DQ3 G8 D9 F-ACC E9 F-WP# F9 A/DQ2 G9 D10 A19 E10 A18 F10 A/DQ9 G10 VCCQ
RFU
D11 A17 E11 F-CE# F11 A/DQ8 G11 A/DQ1 H11
NC
D12 A22 E12 VSSQ F12 OE# G12 A/DQ0 H12
NC
Reserved for Future Use
F-RDY/ R-WAIT
E3 VCCQ F3 VSS G3
A21
E4 A16 F4 A/DQ7 G4
VSS
E5 A20 F5 A/DQ6 G5 VSSQ
CLK
E6 AVD# F6
VCC
E7 DNU F7
Flash/RAM Shared Only
Flash Only
A/DQ13 A/DQ12 G6 A/DQ5 G7 A/DQ4 H7 R-CE#
RAM Only
A/DQ15 A/DQ14 H3
NC
A/DQ11 A/DQ10 H8 R-CRE
H4
RFU
RFU
K3 NC
K14 NC
Notes 1. Addresses are shared between Flash and RAM depending on the density of the pSRAM. 2. CLK and WAIT signals are Flash only for the S71NS064NA0-RT, while on that MCP, the CRE signal won't exist.
MCP S71NS128NC0 S71NS128NB0 S71NS128NA0 S71NS064NB0 S71NS064NA0 S71NS064N80
Flash-Only Addresses A22 A22-A21 A22-A20 A21 A21-A20 A21-A19
Shared Addresses A21-A16 A20-A16 A19-A16
Shared ADQ Pins
ADQ15 - ADQ0 A20-A16 A19-A16 A18-A16
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Data
Sheet
(Advance
Information)
4.2.2
pSRAM Based Pinout, 60-Ball, VFBGA
Figure 4.2 pSRAM Based Pinout, 60-Ball, VFBGA
A1 NC A18 NC
Legend
C3 NC
C16 NC
No Connect (Distance between outer NC balls is 2x pitch)
E5
E6
E9
E10
E13
E14
NC
F5
RFU
F6 F7 F8
R-LB#
F9
R-UB#
F10 WE# G10 F-RST# H10 A/DQ3 J10 F11 F-ACC G11 F-WP# H11 A/DQ2 J11 F12 A19 G12 A18 H12 A/DQ9 J12 VCCQ
RFU
F13 A17 G13 F-CE# H13 A/DQ8 J13 A/DQ1 K13
NC
F14 A22 G14 VSSQ H14 OE# J14 A/DQ0 K14
NC
Reserved for Future Use
F-RDY/ R-WAIT
G5 VCCQ H5 VSS J5
A21
G6 A16 H6 A/DQ7 J6
VSS
G7 A20 H7 A/DQ6 J7 VSSQ
CLK
G8 AVD# H8
VCC
G9 A23 H9
Flash/RAM Shared Only
Flash Only
A/DQ13 A/DQ12 J8 A/DQ5 J9 A/DQ4 K9 R-CE#
RAM Only
A/DQ15 A/DQ14 K5
NC
A/DQ11 A/DQ10 K10 R-CRE
K6
RFU
RFU
M3 NC
M16 NC
P1 NC
P18 NC
Note Addresses are shared between Flash and RAM depending on the density of the pSRAM.
MCP S71NS256NC0 S71NS256NB0
Flash-Only Addresses A23-A22 A23-A21
Shared Addresses A21-A16 A20-A16
Shared ADQ Pins ADQ15-ADQ0 ADQ15-ADQ0
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4.2.3
Look Ahead Connection Diagram
Figure 4.3 112-ball x16 MUX NOR Flash + x16 MUX pSRAM on Shared Bus and x16 NAND Interface ORNAND on Bus 2
1 A NC B NC C NC D NC E DNU F N1-CE# N-RE# F-RDY/ R-WAIT G N-VCC N-VCC H N-VSS J N-CLE K DNU L NC M NC N NC P NC NC NC NC NC NC NC NC NC DNU DNU N-IO0 N-IO8 NC NC N-WE# N-WP# A24 R-CE# R-CRE VSS N-IO1 N-IO9 N-IO2 N-ALE A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 N-IO18 N-IO3 NOR Flash Shared Only N-VSS VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# VCC VSS VCCQ A16 A20 AVD# A23 F-RST# F-WP# A18 F1-CE# VSSQ N-IO11 N-PRE A21 VSS CLK VCC WE# F-ACC A19 A17 A22 N-IO4 N-IO12 ORNAND Flash Only N-RDY N2-CE# F2-CE# R-LB# R-UB# N-IO5 N-IO13 N-IO6 N-IO14 pSRAM Only NC DNU DNU N-IO7 N-IO15 NC NC NOR Flash 1 Only NC NC NC NC NC Do Not Use NC No Connect NC NOR Flash/pSRAM Shared Only 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Legend
NOR Flash 2 Only
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Data
Sheet
(Advance
Information)
4.3
4.3.1
Physical Dimensions
NLB056--9.2 x 8.0 mm, 56-ball VFBGA
Figure 4.4 NLB056--56-ball VFBGA
D
0.10 C (2X)
14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
D1 eD
SE 7 E1
E eE
INDEX MARK PIN A1 CORNER 9
K J HGFEDCBA
B
7
TOP VIEW
0.10 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW
0.20 C
A A2 A1
6
C
0.08 C
SIDE VIEW b
56X
0.15 M C A B 0.08 M C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.25 NLB 056 N/A 9.20 mm x 8.00 mm PACKAGE MIN --0.20 0.85 NOM ------9.20 BSC. 8.00 BSC. 4.50 BSC. 6.50 BSC. 10 14 56 0.30 0.50 BSC. 0.50 BSC 0.25 BSC.
A2 ~ A13,B1 ~ B14 C1,C2,C5,C6,C9,C10,C13,C14 D1,D2,D13,D14,E1,E2,E13,E14,F1,F2,F13,F14 G1,G2,G13,G14,H1,H2,H5,H6,H9,H10,H13,H14 J1 ~ J14, K2 ~ K13
1. 2. 3. NOTE PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT 0.35 BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9 8. 7 6 4. 5.
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
MAX 1.20 --0.97
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3507\ 16-038.22 \ 7.14.5
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4.3.2
NLA060--11.0 x 10.0 mm, 60-ball VFBGA
Figure 4.5 NLA060--60-ball VFBGA
D
0.15 C (2X)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
D1 eD
SE
7
E eE
E1
INDEX MARK PIN A1 CORNER 9
P N ML K J H GF E D C B A
B
7
TOP VIEW A A2 A1
6
0.15 C (2X) 0.20 C
SD
PIN A1 CORNER
BOTTOM VIEW
C
0.08 C
SIDE VIEW b
60X
0.15 0.08
M C AB MC
NOTES:
PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.25
NLA 060 N/A 10.95 mm x 9.95 mm PACKAGE MIN --0.20 0.85 NOM ------10.95 BSC. 9.95 BSC. 6.50 BSC. 8.50 BSC. 14 18 60 0.30 0.50 BSC. 0.50 BSC 0.25 BSC.
A2~A17,B1~B18,C1,C2,C4~C15,C17,C18 D1~D18,E1,E2,E3,E4,E7,E8,E11,E12,E15,E16,E17,E18 F1,F2,F3,F4,F15,F16,F17,F18,G1,G2,G3,G4,G15,G16,G17,G18 H1,H2,H3,H4,H15,H16,H17,H18,J1,J2,J3,J4,J15,J16,J17,J18 K1,K2,K3,K4,K7,K8,K11,K12,K15,K16,K17,K18 L1 ~L18,M1,M2,M4~M15,M17,M18,N1~N18,P2~P17
1. 2. 3. NOTE PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT 0.35 BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 6 7 4. 5.
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3483 \ 16-038.22 \ 3.11.5
MAX 1.20 --0.97
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
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5. Revision History
Section Revision A (January 3, 2006) Initial Release under Publication Identification Number S71NS128NC0_01 Revision A1 (March 1, 2006) Global Revision A2 (June 13, 2006) Connection Diagrams Revision A3 (October 10, 2006) Global Revision A4 (December 22, 2006) Added S71NS064NA0-RA, S71NS064N80-RA Global Revision A5 (March 2, 2007) Ordering Information Revision A6 (December 19, 2007) Global Revision A7 (March 26, 2008) Ordering Information Added Low-Halogen package option for NS064N MCPs Added Note 2 for NS128N and NS256N MCPs Added ordering information and valid combinations for S71NS064NB0 Revised Ordering Information and Valid Combinations for S71NS064N80 Deleted S71NS064NA0-RT Added note to recommend S71NS128P and S71NS256P for new designs Added the S71NS064NA0-RT - the one using pSRAM Type 2 Corrected the grid reference for 56-ball connection diagram Changed the Publication Identification Number from S71NS128NC0_01 to S71NS-N_00 Added the MCP S71NS064NA0 Description
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Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2007-2008 Spansion Inc. All rights reserved. Spansion(R), the Spansion Logo, MirrorBit(R), MirrorBit(R) EclipseTM, ORNANDTM, ORNAND2TM, HD-SIMTM and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.
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